The present invention is directed to bipolar transistor logic gates, and more particularly to gates of this type that combine high speed operation with high packing density.
Logic gates that are constructed utilizing Schottky transistor logic (STL) are noted for their high switching speeds, and find utility in a number of applications because of this characteristic. Basically, an STL gate comprises a Schottky transistor, i.e., a bipolar transistor with a Schottky diode clamp between its base and collector. The cathodes of a plurality of Schottky diodes are each connected to the collector of the Schottky transistor, and their anodes comprise the output terminals for the gate. In operation, the clamp between the base and collector of the Schottky transistor prevents this transistor from going into saturation. Consequently, the transistor is quick to respond to changes in the voltage levels at its base. Further information regarding the features and operating characteristics of an STL gate can be found in the article "STL Technology" by Ben J. Sloan, IEDM Technical Digest 1979, pp. 324327.
While STL gates are desirable from the standpoint of their high switching speed, one drawback that has heretofore been associated with them is the comparatively large area that is required for each gate, resulting in a low packing density on a chip. More particularly, in a conventional STL gate, each of the output Schottky diodes is formed on a separate island on the chip, which increases the area of the buried layer for the chip and adds to the isolation area on the chip. The higher the fan-out for each gate, the greater the number of islands that must be provided per gate. For example, a conventional STL gate having a fan-out of four requires five islands, one for each of the four Schottky diodes and one for the transistor collector. The need to provide each of these separate areas on the chip limits the packing density that can be obtained.